I. Field of the Invention
The present invention relates to the field of computer systems. More specifically, the present invention relates to memory access in computer systems.
II. Backaround Information
Relative to the speed of host processors, system dynamic random access memory (DRAM) memory is typically quite slow. Whenever the processor accesses DRAM, wait states are inserted in each bus cycle. This diminishes the performance of the processor in the system. To improve the performance of the processor, a relatively small amount of high-speed static RAM (cache) is positioned between the processor and DRAM memory. A device referred to as a cache controller attempts to keep copies of information that the processor may request in its cache. The cache controller maintains a directory to track information currently in the cache. Whenever the processor initiates a memory read, the cache controller performs a very quick search of the directory to determine if the requested information is already in the cache. When the requested information is in the cache, a "hit" occurs. When the requested information is not in the cache, a "miss" occurs.
When a hit occurs, the controller accesses the cache memory to get the requested information, routes it to the processor, and informs the processor of the presence of the data on the bus. Quick directory search and fast access time of the static RAM (cache) guarantees the processor fast access to the requested information. When a miss occurs, the memory controller accesses the DRAM to get the requested data. One or more wait states are inserted in the processor's bus cycle. Whenever the cache controller is forced to go to DRAM to get information, it always gets an object of a fixed size from memory. This is referred to as a "line" of information. The size of a line is defined by cache controller design. When the controller retrieves the line from DRAM memory, it supplies the line containing the originally requested data to the processor and also records the entire line in the external cache (if one is present). If the processor has an internal cache, as most processors do, the entire line is also supplied to the processor for storage in its internal cache.
A cache controller that resides between its associated processor and the rest of the world is referred to as a look-through cache controller. Look-through cache controllers are divided into two categories: write-through and write-back. A write-back cache controller handles memory write operations as follows: on a write hit, it updates the line in cache but not in DRAM. It then marks the line as dirty, or modified, in the cache directory. This means that the line no longer mirrors its associated line in DRAM memory. Of the two lines, the cache line is current and the memory line is stale.
On a write miss, the controller typically only updates the line in memory. If the contents of the cache mirrors the information in memory the cache is called as coherent or consistent. The write-back cache's handling of memory write hits allows the cache and the memory contents to become desynchronized or inconsistent.
Whenever the CPU or any other master in the system generates an access to shared memory, that access is snooped by other agents in the system. The term "snoop" means that the cache latches the line address and looks it up to determine if it has a copy of the line being accessed. If the access hits a modified line, the agent that owns the exclusive copy of that line initiates a write-back to main memory. The term "write-back" is used when the processor has a version in its cache, of whatever should be in the memory, and is in a modified state, which means that the memory in the processor is the most coherent. When a PCI bus master drives a write to memory, and it happens to hit the cache location, the processors needs to evict the most coherent memory such that it does not override the original write. In this case the write is the most coherent while the write-back inside the cache is less coherent.
Generally, a write-back operation is performed to the memory before the PCI write is performed to the DRAM. This policy allows the write operation to override the write back as the write operation is the most coherent piece of knowledge, since the write is the last thing that happens to the DRAM.
It is desirable to provide a way in which one may first write to the system memory and then write-back to the system memory without losing the most coherent information. This is because on a bus such as the P6 bus in a Pentium.RTM. Processor manufactured by Intel Corporation of Santa Clara, Calif., the write data is always transferred before the write back data. Sending write data to memory first may reduce delays in the pipeline.